While FET's have uses throughout the microelectronics field, a major application is in memory cells for storage of data. According to standard industry practice, memory cells are currently formed in semiconductor materials such as silicon by a combination of an FET transistor and a capacitor which may, for example, be deep-etched into the silicon nearby and can store electric charge. While such memory cells, when combined to form DRAM's (Dynamic Random Access Memory) and SRAM's (Static Random Access Memory), now dominate fast-access data storage in computer systems, they have a major drawback--they lose all their information when the power is removed. As a result, there has been a very strong interest in creating nonvolatile memory for low power applications. As is well known, FET's are also used in EEPROM, Flash memory and other non-volatile memory applications.
Single-transistor memory cells using ferroelectric materials were first proposed in the 1960's and have been pursued since the early 1970's. These materials provide a means for nonvolatile information storage because of the inherent stability of the two ferroelectric polarization states. It is thought that the polarization charge of a ferroelectric material could be used to change the surface conductivity of a semiconductor material. In effect, such ferroelectric FET's would store information using the polarization direction, rather than using an excess electron charge on a capacitor or a floating gate--the current industry standard for memory cells. Because of their non volatility and their fast switching speeds (&lt;1 ns), ferroelectrics have become attractive candidates for future generations of DRAM. Recently, several designs for ferroelectric memory transistors have been proposed that have significant shortcomings which limit their effectiveness for low-voltage, high-speed, high-density (i.e. DRAM-like) memory applications.
FIG. 1 (prior art) illustrates the operating principle of a ferroelectric memory transistor. The device 1 is essentially a MOSFET with a piece of ferroelectric material 2 positioned somewhere above the Si channel 3c between source 3s and drain 3d. When the ferroelectric is polarized in one direction 4 ("downward" as depicted in FIG. 1(a)), a read voltage V.sub.gs applied to the gate 5 induces an inversion layer in the transistor channel. If a voltage bias is placed across the source-drain, a current will flow through the transistor. A different case is shown in prior art FIG. 1(b), where the ferroelectric is polarized in the opposite direction 6. Because the ferroelectric is polarized differently, the same read voltage V.sub.gs applied to the gate does not induce an inversion layer for conduction in the channel 3c, and so little current flows. The threshold voltage of the transistor is thus controlled via the direction of ferroelectric polarization. An attractive feature of this type of device is that information is stored in the polarization state of the ferroelectric, and so the information remains undisturbed when power is removed from the device.
Attempts to reduce this principle to practice have followed two main avenues. In the first design, the ferroelectric material is either placed directly on the Si transistor channel (as described in Rost et al, in Appl. Phys. Lett. 59, 3654, 1991 and in Sugubuchi et al., in J. Appl. Phys. 46, 2877, 1975), or alternatively on a dielectric layer which itself covers the channel (for example, see Chen et al in Appl. Phys. Lett. 69, 3275, 1996, Tokumitsu et al in IEEE Electron Device Letters 18, 160, 1997, Yu et al at Appl. Phys. Lett. 70, 490, 1997, and Hirai et al at Jpn. J. Appl. Phys. 33, 5219, 1994). This device geometry results in a strong electrostatic coupling between the top gate and the channel. Although this device design has several attractive features, it suffers severe fabrication difficulties, including diffusion of the ferroelectric into the Si channel, and uncontrolled formation of thin SiO.sub.2 layers at the Si/ferroelectric interface during thermal treatments. As a result of problems introduced by these fabrication issues, devices of this type have shown slow switching speeds (see Tokumitsu et al, supra, and Sugibuchi et al, supra), high operating voltages (see Chen et al supra, Tokumitsu et al, supra, Rost et al, supra, and Sugibuchi et al, supra), and poor memory retention characteristics (see Yu et al, supra, and Hirai et al, supra).
FIG. 2 (prior art) shows a second (and more promising) design of a ferroelectric FET for use in memory applications, as described in Chen et al, supra, Nakamura et al at IEDM, 68, 1995, and in U.S. Pat. No. 5,365,094, issued Nov. 15, 1994 to H. Takasu). In this device, an electrically conducting (e.g. metal) floating gate 7 is inserted between the ferroelectric film 2 and a bottom gate insulator 8 (which is typically SiO.sub.2). From a fabrication standpoint, this device is attractive because the ferroelectric is separated from the Si channel by both the floating gate and a SiO.sub.2 layer. A suitable floating gate material (e.g. Pt or Ir ) can be used to prevent diffusion of the ferroelectric material into the channel.
A main drawback of this type of structure is the high voltage required for changing the polarization of the ferroelectric. By adding the SiO.sub.2 and floating gate layers to the gate stack, the ferroelectric becomes much more weakly coupled to the Si channel. For a given voltage applied to the gate only a fraction of V.sub.gs is applied across the ferroelectric (and thus only a fraction of the applied voltage is available for writing the cell). Ferroelectric materials have large dielectric constants (typically between about 100-500) compared to SiO.sub.2 (about 3.9), which means that to sustain a reasonable voltage across the ferroelectric, a significantly higher voltage must be applied to the gate. In general the voltage required to write information to this device is much larger than that necessary for reading. All devices of this type built to date use operating voltages in excess of 5 V (see Chen et al, supra, and U.S. Pat. No. 5,365,094), while for high-density memory applications, the maximum operating voltages should be less than 3V.
One interesting proposal has been to use a high-dielectric constant material (such as barium strontium titanate) in place of the SiO.sub.2 layer 8, to more closely match the dielectric constants of the two insulators in the gate stack (see Tokumitsu et al, supra, and U.S. Pat. No. 5,365,094). This would enable a the memory device to function at lower voltages, although it introduces problems in fabrication similar to those discussed above with regard to the first type of ferroelectric FET design. Even with more closely matched dielectrics however, it is still impossible to use the entire gate voltage V.sub.gs for writing the memory cell.